1. Field of the Invention
The invention relates to the field of designing inductors and inductor circuits particularly for integrated circuits.
2. Prior Art
There is a growing need for optimally designed inductors and integrated circuit, as radio-frequency integrated circuits (RFICs) become more widely used in low-cost communications. This, for instance, has created great demand and interest in on-chips spiral inductors. The parasitic resistance and capacitance associated with these spiral inductors result in several engineering trade-offs. Unfortunately, no inductor optimization tool exists to aid in circuit design. Currently most designers are limited to use of a library of previously fabricated inductors or generating a large database of inductors using a 3-D field solver. While the former option severely constrains the available design space, the latter one requires a sophisticated search engine and is numerically expensive, especially when process parameters change. Moreover, neither approach is amenable to the application dependent nature of inductor design. For example, while a resonator requires an inductor that maximizes the magnitude of the impedance at the resonant frequency (subject to a specific load capacitance), a shunt-peaked amplifier requires one that maximizes bandwidth. Consequently, the optimal layout of these inductors is determined by the design goals.
A variety of limited computer-aided-design (CAD) tools have been developed for analog circuit design, including optimization tools. In general, these tools do not provide good results for inductors in integrated circuits.
The TILOS optimization system applies geometric programming to digital circuit design, and more specifically to transistor and wire sizing for Elmore delay minimization, as described in U.S. Pat. No. 4,827,428. The geometric programs that arise in Elmore delay minimization are very specialized (the only exponents that arise are 0 and .+-.1). Furthermore, the representation of the problem as a geometric program is only approximate (since the actual circuits are nonlinear, and the threshold delay, not Elmore delay, is the true objective).
Thus, an improved optimization method that quickly generates globally optimal designs for an inductor and inductor circuits is needed.